As the improvement on production technology for semiconductor integrated circuits, high integration and high-speed performance of semiconductor devices are demanded. Accordingly, since stricter flatness is demanded for the surfaces of semiconductor substrates in production processes of fine circuits in semiconductor devices, Chemical Mechanical Polishing (CMP) has been an essential technology for production processes of semiconductor devices.
This CMP is used for a wiring process in which grooves formed on an insulation layer of a semiconductor substrate is filled with metal material such as tungsten, copper, or aluminum, and the metal layer piled at groove portions are polished and removed (see Patent Document 1). In recent semiconductor memory devices, it has been investigated to use metal material for device portions such as gate electrodes, too, in order to further improve the performances. CMP is used in the production process of this semiconductor memory device as well (see Patent Document 2).
In CMP, a semiconductor substrate is pressed against a polishing pad attached onto a turn table, while the polishing pad is made to move relatively as the polishing pad is supplied with a polishing composition containing abrasive grains and a reagent. In this process, it is possible to grind unevenness on the surface of the semiconductor substrate on the basis of a chemical reaction due to the reagent and a mechanical polishing effect due to the abrasive grains to flatten the surface. As the abrasive grains contained in a polishing composition, inorganic particles of silicon dioxide, aluminum oxide, silicon carbide, diamond, titanium oxide, zirconium oxide, cerium oxide, manganese oxide, and so on are used (see Patent Documents 3 and 4).
In CMP process, important characteristics are polishing speed and defects due to polishing process such as a scratch and dishing, which is a concave on a buried pattern portion. Since polishing speed relates to productivity in a semiconductor producing process, and productivity influences to the cost of a semiconductor device, higher polishing speed is required. On the other hand, since defects influence to the yield and reliability of a semiconductor device, the problem is how to suppress defect generation in a CMP process. As described above, a polishing process on a higher level comes to be demanded in accordance with miniaturization of semiconductor devices.